The increasing sophistication (higher-speed operation, higher density) of LSIs accelerates the lowering of a power supply voltage, thus making it more difficult to suppress a voltage drop in feed wiring on a printed board.
For example, VLSIs whose power supply voltage is 1 V and power consumption is 40 to 50 W have been put into the market in recent years. In this case, a power supply current is 40 to 50 A. Supposing that the application range of 1 V is ±5%, a permissible voltage drop is 50 mV or less. At present, however, it is difficult to establish a design method for realizing this goal.
Examples of the related art of feed wiring are Japanese Unexamined Patent Application Publication (JP-A) Nos. Hei 10-270862 and 2005-183790. Both the technologies are aimed at suppressing electromagnetic interference (EMI) by inserting a slit in the vicinity of an LSI to separate a high frequency component. In the technologies, however, feed wiring from an on-board power source to the LSI is not considered, and hence there is a problem in that it is ineffective in suppressing a DC voltage drop.